Modern computer packaging technology provides for a modular design that may be used in a variety of computer system products in conjunction with a computer memory. In one example, multiple processor cores may be packaged on a single module or chip die. In another example, multiple chip cores may be packaged with storage control function on a single module or chip die. In an embodiment, the multiple processor cores employ a cache hierarchy on the module or chip die. In one embodiment, only a single core of the module or chip die may be used in a computer system. In one embodiment, only a single such module or chip die may be used in a computer system. In one embodiment, multiple such modules or chip dies may be used in a computer system. Each embodiment may require a different cache coherency protocol to efficiently perform desired function and achieve desired performance.
U.S. Pat. No. 8,423,736 “MAINTAINING CACHE COHERENCE IN A MULTI-NODE, SYMMETRIC MULTIPROCESSING COMPUTER”, filed 2010-06-16 and incorporated by reference herein, teaches “Maintaining cache coherence in a multi-node, symmetric multiprocessing computer, the computer composed of a plurality of compute nodes, including, broadcasting upon a cache miss by a first compute node a request for a cache line; transmitting from each of the other compute nodes to all other nodes the state of the cache line on that node, including transmitting from any compute node having a correct copy to the first node the correct copy of the cache line; and updating by each node the state of the cache line in each node, in dependence upon one or more of the states of the cache line in all the nodes.”
U.S. Pat. No. 8,402,225 “METHOD FOR PERFORMING CACHE COHERENCY IN A COMPUTER SYSTEM”, filed 2010-09-21 and incorporated by reference herein, teaches “in a computing system, cache coherency is performed by selecting one of a plurality of coherency protocols for a first memory transaction. Each of the plurality of coherency protocols has a unique set of cache states that may be applied to cached data for the first memory transaction. Cache coherency is performed on appropriate caches in the computing system by applying the set of cache states of the selected one of the plurality of coherency protocols.”
U.S. Pat. No. 8,010,716 “METHODS AND APPARATUS FOR SUPPORTING MULTIPLE CONFIGURATIONS IN A MULTI-PROCESSOR SYSTEM”, filed 2010-08-18 and incorporated by reference herein, teaches “methods and apparatus provide for interconnecting one or more multiprocessors and one or more external devices through one or more configurable interface circuits, which are adapted for operation in: (i) a first mode to provide a coherent symmetric interface; or (ii) a second mode to provide a non-coherent interface.
U.S. Patent Application Publication No 2004/0044850 titled “Method and Apparatus for the Synchronization of Distributed Caches” filed 2002-08-28 incorporated herein by reference in its entirety, teaches a hierarchical caching protocol suitable for use with distributed caches, including use within a caching input/output hub.